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CIS >> Services >> Digital IC Design Engineering

Digital ASIC VLSI Synthesis and Routing Engineering Services

The staff at CIS has broad experience designing ASICs using a wide range of EDA tools. CIS staff works with either the client's tools or CIS' tools, as needed.

An example of our many successful tapeouts was a 0.18u mixed mode 5 metal layer design with 7.5 million gates (4 million standard cell gates), over 100 memory blocks, 4 PLLs and a DAC in a 23 mm2 core area and with a maximum clock speed of 200 MHz.

A typical ASIC layout design flow:
Logic Synthesis (translation of the behavioral to structural Verilog code)
     
Note: our customers often perform this step.
Floor planning and placement of I/O and major macro blocks (ROMs, RAMs, PLLs, etc.)
Timing driven Place and Route of standard cells
Clock Tree Synthesis, Timing Analysis
Layout editing as needed
Delay Calculation (SDF output)
Back-annotation of post layout timing delays
Final timing check
Physical verification (DRC, LVS< EDS-Latch up, Soft-tie/ERC, Stress, Antenna)

ASIC Design Step

Tools Used and Mastered by CIS

Synthesis and Optimization

Mentor Graphics (MG) Leonardo

Floor Planning

Avant! Apollo, Silicon Valley Research (SVR) GARDS

Place and Route

Avant! Apollo, Silicon Valley Research (SVR) GARDS

Layout Editing

Cadence Virtuoso, MG IC Station, IC Editors ICED

Physical Verification

MG Calibre, Cadence Dracula

Timing Analysis

Avant! Apollo, MG Leonardo

Verilog Logic Simulation

SimuCAD Silos

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